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KAIST Controls Where 2D Semiconductor Crystals Begin to Grow, Addressing a Key Challenge in Stacking AI Chips
Two-dimensional (2D) semiconductors, only a few atomic layers thick, are a promising material for making AI chips faster and more energy efficient by stacking additional semiconductor layers on top of existing computing circuits. However, when crystals form at multiple random locations during growth, it is difficult to produce high-quality semiconductors at the desired positions. A KAIST joint research team has developed a technology that sets in advance where a crystal begins to grow and allows only one crystal to grow at that position. By controlling the starting point of semiconductor growth, the work addresses a key challenge in realizing next-generation stacked semiconductors.
KAIST announced that a research team led by Professor Kibum Kang from the Department of Materials Science and Engineering, in collaboration with UNIST, Hanyang University, and TDS Innovation (Co-CEOs Kibum Kang and Sanghyun Mo), has developed a new growth technique that precisely controls the location of nucleation, the stage at which 2D semiconductor crystals first form, using chemical species released from an oxide barrier.
When AI generates responses or processes large amounts of data, time and power are consumed not only by computation but also by moving data within the chip. Stacking the devices used for computation and data storage vertically, so that they are placed close together, shortens the distance that data must travel and can reduce processing delays and power consumption. This requires a technology that forms high-quality semiconductors directly at the required positions on top of circuits that have already been fabricated.
Deposited semiconductors, in which devices are made by forming a thin film of semiconductor material directly on the required surface, are a promising technology for building stacked chips. 2D semiconductors are particularly well suited for stacking thin device layers because they retain the electrical properties of a semiconductor while being only a few atomic layers thick.
The challenge is that, as a thin semiconductor film grows, the positions where crystals begin to form are inherently random. A crystal is a structure in which the atoms that make up the semiconductor are arranged in a regular, repeating pattern. When crystals grow separately from several locations and meet, grain boundaries form between them. These boundaries hinder the movement of electrons and can degrade the quality of the semiconductor.
Area-selective growth techniques, which define in advance the regions where a semiconductor will grow, already existed. However, it has been difficult to control exactly where crystals first form within those regions and how many of them form. The research team achieved deterministic nucleation, in which nucleation that previously occurred at random takes place one at a time at defined positions. In addition to defining the region where the semiconductor will grow, the team also determined the point within that region where growth begins.
The researchers named the technique etching-flux-mediated single-centered nucleation (EF-SCN). The key element is oxygen released from an oxide barrier, such as hafnium oxide (HfO₂), that surrounds the growth region. This oxygen acts as an etching flux that suppresses the formation of crystal nuclei of molybdenum disulfide (MoS₂), a representative 2D semiconductor. Etching refers to chemically removing material, and flux refers to the flow of a specific chemical species that is transported and supplied in a way that affects nearby chemical reactions.
The suppressing effect is strong at the edges near the oxide barrier and becomes weaker toward the center, which is farthest from the barrier. Using this difference, the team caused a single crystal to begin growing at only one point in the center. While the crystal that started at the center continued to grow, the formation of new crystals around it was also suppressed, so that the single crystal could grow larger.
In experiments, the team grew one MoS₂ single crystal at a designated central position in more than 99% of 400 different patterns. A single crystal has one continuous atomic arrangement, and because it reduces the boundaries that form where multiple crystals meet, it is advantageous for producing high-quality semiconductors. Using MoS₂–MoSe₂ lateral heterostructures grown with this method, the team also deposited a thin film of ruthenium (Ru) metal selectively on the molybdenum diselenide (MoSe₂) regions only. The researchers further analyzed the principle behind this position control through growth experiments and simulations.
The significance of this work is that it turns the starting point of semiconductor thin-film growth, which had been determined at random, into a process parameter that can be designed. Instead of fabricating 2D semiconductors elsewhere and then transferring them, this approach could lead to a manufacturing technology that grows high-quality semiconductors directly at the required positions on a chip. Deposited semiconductors are expected to be adopted in the 2030s to improve the performance and lower the power consumption of AI chips. If applied to stacked AI chips, the technology could reduce the time and energy spent on moving data, which would shorten the time users wait for AI responses and reduce the power demands of data centers.
“In thin-film growth, where a crystal forms is inherently a matter of probability, and the key significance of this study is that it allows that starting point to be determined at a desired position,” said Professor Kibum Kang. Professor Kang added that the technology will serve as the basis for stacked-channel processes, in which semiconductor devices are stacked vertically, by growing high-quality 2D semiconductors directly where they are needed.
“In 2D semiconductors, the position where growth begins can change in response to even small chemical changes in the surroundings,” said Dr. Jeongwon Park, a co-first author. Park explained that the significance of the study lies in using this property to control where the semiconductor begins to grow.
Dr. Park and master’s student Jiyun Kim from the KAIST Department of Materials Science and Engineering, Sumin Kang, who received a master’s degree from the same department, integrated M.S.–Ph.D. student Jieun Oh from the Department of Materials Science and Chemical Engineering at Hanyang University, and integrated M.S.–Ph.D. student Youngmin Sunwoo from the Graduate School of Semiconductor Materials and Devices Engineering at UNIST participated as co-first authors. The findings were published in Nature on October 8.
Paper title: Spatially deterministic nucleation of 2D semiconductors by etching flux
DOI: 10.1038/s41586-026-11095-1
This research was supported by the Nano and Material Technology Development Program and the Basic Science Research Program of the National Research Foundation of Korea (NRF), funded by the Ministry of Science and ICT (MSIT). Additional support was provided by the International Cooperation Program for Source Technology Development, the Development of vdW Materials and Process Technologies for Ultra-High-Density Semiconductors Program, the Next-Generation Intelligent Semiconductor Technology Development Program, the Ministry of Trade, Industry and Energy (MOTIE), the Korea Institute for Advancement of Technology (KIAT), the Commercialization Promotion Agency for R&D Outcomes (COMPA), the Innopolis Foundation, the Ministry of SMEs and Startups (MSS), and NVIDIA.
2026.10.13 View 386 -
KAIST Develops AI Chip That Recognizes Changes in Motion over Time
For a wearable device to distinguish walking from a brief swing of the arm, it must recognize how a movement changes over time. Korean researchers have developed a technology that stacks semiconductor devices with different response speeds, allowing them to recognize both a change that has just occurred and the changes before it. The technology could be applied to small devices that are worn on or attached to the body to analyze movement and physiological signals.
KAIST (President Choongsik Bae) announced on September 29 that a research team led by Professor Jimin Kwon from the Department of AI Systems, together with researchers from UNIST (President Chong Rae Park) and POSTECH (President Seong Keun Kim), has made a solid thin film from a material that contains ions and used it to stack semiconductor devices with different response speeds in multiple layers.
In these devices, applying a voltage moves the ions within the material and changes the flow of current. When the voltage is removed, the ions require time to return to their original state. As a result, the effect of previous signals remains in the device for a short time. This slow movement has generally been considered a disadvantage, but the research team used it to identify earlier inputs.
The main challenge was controlling how long this effect lasts. Until now, such materials have mostly been liquids or soft gels, which made it difficult to fabricate the devices precisely or to stack them in multiple layers.
To address this challenge, the team made the material into a solid thin film, known as a solid-state ionogel, and adjusted the amount of ions in the film as well as its thickness. This allowed them to create devices that respond to signals either quickly or slowly. When the two types were stacked, one layer responded to the most recent signal, while the other responded to signals that had accumulated over a longer period.
The researchers confirmed that the devices could distinguish all 16 patterns created when four consecutive input signals are turned on or off in different combinations. Using the responses measured from the devices, they also built a simulation model of a system that classifies videos of moving handwritten digits. The model achieved validation accuracies above 90% for sequences of moving images played at different speeds.
The team fabricated the devices on both 4-inch wafers and flexible substrates. Their electrical characteristics remained stable for 55 months after fabrication.
The results could be used to develop technologies for processing information that changes over time, such as movement and signals from the body, directly on small devices. Further validation is needed to determine how the technology performs, and how much power it saves, in actual smartwatches.
"These devices can be fabricated on large-area substrates using existing thin-film semiconductor processes, and they can also be stacked in multiple layers," said Professor Kwon. He added that the technology could be developed into AI chips that analyze movement and physiological signals for devices that must operate with low power consumption, such as smartwatches.
Research Professor Haksoon Jung from KAIST is the first author of the study, and Professor Yong-Young Noh of POSTECH and Professor Jimin Kwon of KAIST are the co-corresponding authors. The findings were published in Advanced Materials on June 30.
Paper title: Monolithic 3D-Integrated All-Solid Ion-Gated Carbon Nanotube Transistors With Tunable Ionic Conductance for Multi-Timescale Reservoir Computing,
DOI: 10.1002/adma.202523703
This research was supported by the National R&D Program through the National Research Foundation of Korea (NRF), funded by the Korean government (Ministry of Science and ICT, MSIT) (RS-2023-00281195 and RS-2024-00355384), and by the Korea Planning & Evaluation Institute of Industrial Technology (KEIT), funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) (RS-2024-00417909).
2026.09.29 View 1077 -
KAIST Extends Lifespan of Graphite-Free Anode-Free Batteries That Could Make EV Batteries Smaller and Lighter
Korean researchers have developed a technology that could make electric-vehicle (EV) batteries smaller and lighter while helping EVs travel farther on a single charge. A KAIST research team has proposed a new solution to a persistent problem in anode-free batteries, which reduce weight and volume by eliminating anode materials such as graphite that normally store lithium during charging. In these batteries, lithium can grow into sharp, spike-like structures that shorten battery life. The key lies in using nanofabrication techniques employed in semiconductor manufacturing to create uniform sites for lithium deposition and promote the formation of a robust protective layer.
KAIST (President Choongsik Bae) announced on September 22 that a joint research team led by Professors Jinwoo Lee and Hee-Tae Jung from the Department of Chemical and Biomolecular Engineering, working with researchers from Kyungpook National University (President Heo Young-woo) and the National NanoFab Center (President Park Heung Soo), has developed a new technology that extends the lifespan of anode-free batteries by applying the ultrafine fabrication processes used in semiconductor device manufacturing to batteries.
Conventional lithium-ion batteries store lithium in an anode material such as graphite during charging. Anode-free batteries, by contrast, deposit lithium directly onto a thin copper foil without a separate anode material. Because they eliminate the weight and volume that the anode material would otherwise occupy, they are drawing attention as a next-generation technology capable of packing more energy into a battery of the same size.
However, repeated charging and discharging cause lithium to deposit unevenly on the copper foil, growing into branch- or spike-like structures known as dendrites. The protective layer over the lithium also becomes unstable, causing the battery’s performance and lifespan to deteriorate rapidly. This is one of the most significant obstacles standing in the way of commercializing anode-free batteries.
Some previous approaches to extending the lifespan of anode-free batteries involved adding excess lithium or applying a thick protective layer to the surface. These methods provide extra lithium to compensate for losses during use or coat the surface with a protective film. However, adding more material makes the battery heavier and thicker, undercutting the very advantage of a small, lightweight anode-free battery.
To minimize added weight and volume, the research team modified the copper foil on which lithium is deposited. Much like marking out closely spaced parking bays in a flat lot, the team created an array of microscopic tube-shaped structures on the copper surface so that lithium spreads out and deposits evenly rather than concentrating in one spot.
To do this, the team used a process called secondary sputtering lithography (SSL), used for the precise micromachining of semiconductors. Fabricating microscopic tubes about 300 nanometers in diameter and 150 nanometers in height on the copper foil increased the surface area available for lithium deposition to about four times that of flat copper foil, helping to reduce localized, spike-like lithium growth.
The team then coated the copper foil with a roughly 10-nanometer-thick layer of MXene, a two-dimensional material, forming an ultrathin film only a few thousandths the thickness of a human hair. Rather than serving as a finished protective layer itself, the MXene acts like a primer that draws together the components needed to form one. In the LiPF6-based electrolyte used in the study, the MXene surface promotes the formation of a robust protective layer rich in lithium fluoride (LiF) as the battery operates.
This protective layer reduces unwanted reactions between the lithium and the electrolyte and also suppresses the spike-like growth of lithium. By examining electrode surfaces and cross sections while minimizing air exposure, the research team confirmed that a nanoscale protective layer forms uniformly along the MXene and identified the mechanism behind its formation. The analysis employed X-ray photoelectron spectroscopy (XPS), time-of-flight secondary ion mass spectrometry (ToF-SIMS), and transmission electron microscopy (TEM), among other techniques.
Professor Jinwoo Lee said, “This study shows how ultrafine fabrication techniques used in semiconductor manufacturing can create both uniform sites for lithium deposition and a stable protective layer without changing the bulk electrolyte formulation or adding excess lithium.” He added that the technology is expected to serve as a foundation for accelerating the commercialization of high-energy anode-free batteries by extending battery life while minimizing increases in weight and volume.
KAIST researchers Eunji Kim, Hyunju Jung, and Jinuk Kim participated as co-first authors on the study. The findings were published online in the international journal Advanced Functional Materials on September 1.
Paper title: Anion-Interactive Anode Interfaces for Stable Anode-Free Lithium Metal Batteries,
DOI 10.1002/adfm.77931
Author information: Eunji Kim (KAIST/National NanoFab Center, co-first author), Hyunju Jung (KAIST, co-first author), Jinuk Kim (KAIST, co-first author), Hee-Tae Jung (KAIST, corresponding author), Yonghee Lee (Kyungpook National University, corresponding author), Jinwoo Lee (KAIST, corresponding author)
This research was supported by the Nano&Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (RS-2026-25542167), as well as the Global Semiconductor Advanced Fab Utilization Project through the National Nano Fab Center (NNFC). This work was also supported by Semiconductor-Secondary Battery Interfacing Platform Technology Development Project of NNFC.
2026.09.22 View 2983 -
Single Material Enables Efficient Charge Injection into Two Types of Ultrathin Semiconductors, Paving the Way for Smaller, More Energy-Efficient AI Chips
A new approach could help make future AI chips smaller and more energy-efficient. A KAIST-led research team has used a single material to address one of the major obstacles facing atomically thin semiconductors, the difficulty of efficiently injecting charge. The technology could contribute to next-generation AI and low-power semiconductor devices in which multiple ultrathin layers are vertically integrated to increase device density and performance.
KAIST (President Choongsik Bae) announced on September 16 that a research team led by Professor Joonki Suh from the Department of Chemical and Biomolecular Engineering has developed a ‘universal van der Waals tunneling injector’ based on tin diselenide (SnSe2). The single-material injector efficiently supplies charge to two different types of atomically thin semiconductor channels.
The study was conducted in collaboration with researchers from Yonsei University, the Beijing Computational Science Research Center in China, the Korea Institute of Science and Technology (KIST), Hanyang University, the Ulsan National Institute of Science and Technology (UNIST), and Samsung Electronics.
A transistor is a microscopic switch that controls the flow of electric current. Nearly every semiconductor chip, from those used in smartphones and computers to advanced AI processors, contains vast numbers of transistors.
Transistors can be broadly classified as n-type or p-type. In n-type transistors, ‘electrons’ carry the current, while in p-type transistors, current is carried by ‘holes’, which are empty electron states that act as positive charge carriers. Modern semiconductor chips combine these two types in complementary metal-oxide-semiconductor, or CMOS, circuits, which enable fast operation while minimizing power consumption.
Two-dimensional semiconductors, which can be less than a nanometer thick, have recently emerged as promising materials for making chips smaller and more energy-efficient. Their atomically thin structure also makes it possible to stack multiple device layers vertically, potentially allowing more transistors to be integrated within the same footprint.
A persistent challenge, however, has been injecting charge efficiently into such ultrathin semiconductors. Depositing a conventional metal electrode directly onto a two-dimensional semiconductor can damage its delicate atomic structure during fabrication. The resulting interface can also create an energy barrier that obstructs the injection of electrons or holes.
In atomically thin semiconductors, the ‘entry point’ for electrical charge has been a major bottleneck limiting transistor performance. Complicating matters further, n-type and p-type channels generally require different contact conditions and have therefore relied on separately optimized electrodes.
The research team addressed this problem using a single material: tin diselenide (SnSe2), a layered semiconductor composed of tin (Sn) and selenium (Se). Instead of forming strong chemical bonds with the semiconductor channel, SnSe2 can be placed in contact with it through weak interatomic attractions known as van der Waals forces. This approach preserves the atomically thin channel and creates a clean, uniform interface.
Crucially, SnSe2 provides a different but favorable charge-injection pathway depending on the semiconductor with which it is paired.
When combined with p-type tungsten diselenide (WSe2), SnSe2 forms a type-III, or ‘broken-gap’, band alignment that enables efficient band-to-band tunneling. In this process, charge carriers pass through an energy barrier quantum mechanically rather than having to acquire enough energy to travel over it. When combined with n-type molybdenum disulfide (MoS2), the same SnSe2 injector forms a different junction. An applied gate field reshapes and narrows the electron-injection barrier, allowing electrons to tunnel through it.
In other words, whereas n-type and p-type transistors previously required separately optimized charge-injection contacts, SnSe2 serves as a single, shared injector that adapts to both channel polarities through different tunneling mechanisms.
The resulting performance improvements were substantial. In p-type WSe2 transistors, the SnSe2 injector increased the maximum drive current by more than 1,000 times compared with conventional nickel electrodes. Drive current refers to the maximum current that a transistor can deliver when switched on.
In n-type MoS₂ transistors, the SnSe2 injector enabled steep switching and an on/off current ratio exceeding one billion (109). This means that the device conducts current effectively in its on state while strongly suppressing current in its off state.
The team also fabricated a CMOS inverter, a basic building block of digital circuits that combines n-type and p-type transistors, and confirmed that it operated reliably in response to repeated input signals.
The key contribution of this research is that it demonstrated a single material can efficiently supply charge to both types of ultrathin semiconductors, moving beyond the conventional approach of using separate electrodes for n-type and p-type devices.
With further advances in direct growth, large-area fabrication, and device integration, two-dimensional semiconductors could eventually be stacked in multiple layers to form three-dimensional chips. Such architectures could accommodate more transistors within the same footprint and perform more functions while consuming less power, contributing to the development of next-generation AI processors and ultra-low-power electronic devices.
“This study demonstrates that efficient charge injection, one of the most challenging bottlenecks in monolayer two-dimensional semiconductors, can be addressed using a single material platform,” said Professor Joonki Suh. “With further advances in direct growth and large-area processing technologies, this approach could accelerate the practical implementation of low-power two-dimensional CMOS integrated circuits.”
The study was led by KAIST PhD candidate Hanbin Cho as first author, with Professor Kyungmin Ko from Yonsei University and Professor Joonki Suh from KAIST serving as co-corresponding authors. The paper was published online on August 12 in the international journal Advanced Materials.
Paper title: “A Universal van der Waals Tunneling Injector for Monolayer CMOS”
DOI: 10.1002/adma.74597Authors: Hanbin Cho of KAIST, first author; Professor Kyungmin Ko of Yonsei University and Professor Joonki Suh of KAIST, co-corresponding authors
This work was primarily supported by Samsung Electronics Co., Ltd. It also received support from Korean funding agencies, including the National Research Foundation of Korea (NRF), funded by the Ministry of Science and ICT and the Ministry of Education.
2026.09.16 View 2619 -
KAIST Tames a Semiconductor Greenhouse Gas 6,000 Times More Potent Than CO₂ with the ‘Power of Disorder’
Among the gases used in semiconductor manufacturing, tetrafluoromethane (CF₄) is a greenhouse gas over 6,000 times more potent than carbon dioxide. A KAIST research team has developed a technology that removes this gas with high efficiency while extending the usable lifetime of the catalyst that helps break it down by harnessing the ‘power of disorder,’ in which mixing multiple metal atoms together actually stabilizes the catalyst’s structure.
KAIST (President Choongsik Bae) announced on September 3 that a research team led by Professor Minkee Choi from the Department of Chemical and Biomolecular Engineering, working in collaboration with researchers from Samsung Electronics, has developed a new catalyst capable of removing CF₄, a greenhouse gas used in processes such as the fabrication of fine semiconductor circuits with high efficiency over long periods of use.
CF₄ is used in processes such as dry etching, in which unwanted portions of a semiconductor wafer are selectively removed to create fine circuit patterns. The problem lies in the CF₄ left over after use. Because its carbon and fluorine atoms are bound together extremely tightly, the gas does not easily decompose, and once released into the atmosphere, it can persist for roughly 50,000 years. Its impact on global warming is also more than 6,000 times greater than that of carbon dioxide.
To prevent CF₄ from being released as is, semiconductor manufacturing sites currently decompose it at high temperatures using steam and a catalyst. A catalyst speeds up chemical reactions, much like those used to reduce pollutants in car exhaust.
However, conventional catalysts have suffered from declining performance the longer they are used. This is because hydrogen fluoride (HF), generated as CF₄ decomposes, combines with moisture to create a highly corrosive environment, causing the catalyst’s fine particles to aggregate or its structure to change. When small catalyst particles clump together into larger masses, the surface area in contact with the CF₄ to be treated shrinks, and performance declines accordingly.
The research team solved this problem, paradoxically, by harnessing the ‘power of disorder.’
Mixing multiple atom types creates a complex, disordered structure that resists phase changes and remains stable. This process is called entropy stabilization. In simple terms, it is a principle in which evenly mixing multiple kinds of atoms makes it difficult for a catalyst to clump together or change into another structure.
Using this principle, the research team evenly incorporated multiple metals — aluminum (Al), zinc (Zn), gallium (Ga), nickel (Ni), and cobalt (Co) — into a single aluminate crystal structure. Aluminate is a material in which several metals are bonded around a basic framework of aluminum and oxygen. Through this approach, the team developed an ‘entropy-stabilized aluminate (ESA) catalyst’ that resists aggregation and structural deformation even under the harsh conditions of high temperature, moisture, and fluorine occurring together.
The performance gap was clear. The new catalyst’s intrinsic activity for decomposing CF₄ was approximately 2.3 times higher than that of a conventional alumina catalyst. Notably, in an accelerated test conducted at about 800°C for 150 hours, the CF₄ conversion of the conventional alumina catalyst dropped from 93% to 48%. The new catalyst, by contrast, maintained a high level, declining only from 98% to 92%. This demonstrated that the catalyst can remove CF₄ with high efficiency while sustaining its performance over extended periods.
The researchers also revealed the decomposition mechanism of CF₄. To do this, they used oxygen isotopes, which allow the movement of oxygen atoms to be tracked. In simple terms, this involves attaching a ‘tag’ to oxygen atoms so that where the oxygen comes from and where it moves to during the reaction can be traced.
The results confirmed that the catalyst first uses the oxygen within its own structure to decompose CF₄, and that the reaction continues as surrounding steam replenishes the oxygen that has been depleted. In effect, the catalyst functions as a kind of ‘oxygen refill system,’ in which steam restores the oxygen the catalyst draws upon. Through this, the research team provided the world’s first experimental confirmation of a CF₄ decomposition process that had previously only been proposed in theory.
The significance of this research goes beyond developing a single catalyst that decomposes CF₄ effectively; it presents a new catalyst design strategy capable of achieving both high decomposition performance and a long service life at the same time. The approach is expected to be applicable to the future development of catalysts for treating a range of semiconductor process gases by varying the types and combinations of metals used.
Professor Choi said, “By applying the principle that disorder in nature can actually make a structure more stable to catalyst design, we achieved both high CF₄ decomposition performance and long-term stability at the same time.” He added, “This work is meaningful in that it presents a new materials design strategy that can be extended to catalysts for treating a range of semiconductor process gases by varying the types and combinations of metals used.”
The study was led by Dr. Seunghyuck Chi, a postdoctoral researcher in KAIST’s Department of Chemical and Biomolecular Engineering, who served as first author, with researchers from Samsung Electronics participating as co-authors. The findings were published in June in the international chemistry journal Angewandte Chemie International Edition.
Paper title: Entropy-Stabilized Aluminate Catalysts that Break the Activity–Stability Tradeoff in CF₄ Hydrolysis,
DOI: 10.1002/anie.6752036
This research was supported by the National Research Foundation of Korea (RS‐2024‐00333937 and RS‐2024‐00405261).
2026.09.03 View 3304 -
KAIST Solves 3D Memory Reliability Problem with "Oxygen Tunnel" Structure, Boosting AI Chip Performance and Reducing Power Consumption
As AI systems become more advanced, memory is required to transfer larger amounts of data at higher speeds. But conventional planar semiconductor scaling is running out of room. A KAIST research team has now addressed a key weakness in three-dimensional, vertically stacked memory devices, opening a new path to faster, more power-efficient AI semiconductors.
KAIST (President Choongsik Bae) announced on August 25 that a research team led by Professor Jimin Kwon from the School of Electrical Engineering has developed a new multilayer interlayer dielectric structure that reduces defects and significantly enhances the performance of oxide vertical channel transistors (VCTs), a next-generation memory device. The study was conducted in collaboration with researchers from UNIST, Yonsei University, and other Korean institutions.
DRAM, which serves as the main memory in computers, has advanced over the past several decades by scaling down device size while reducing power leakage. More recently, vertical channel structures, in which current flows vertically, have become a key technology for increasing memory density.
The challenge is oxygen vacancies — defects caused by the absence of oxygen atoms in the oxide semiconductor — which destabilizes the material's electrical properties. But oxygen cannot simply be supplied without limit: when oxygen is supplied to suppress oxygen vacancies, some of the oxygen tends to migrate further, reaching the metal electrode and oxidizing it, which degrades device performance instead. The channel needed oxygen; the electrode did not. Therefore, selectively controlling oxygen flow became a key challenge.
The KAIST team developed a new multilayer interlayer dielectric consisting of silicon nitride/silicon dioxide/silicon nitride (SiN/SiO₂/SiN), engineered to function as an "oxygen tunnel" that steers oxygen selectively toward the channel while blocking its path to the electrode. The structure enabled stable compensation of oxygen vacancies in the oxide semiconductor while simultaneously suppressing unwanted oxidation at the electrode, thereby resolving the trade-off.
As a result, the researchers achieved world-class current density and data retention time in oxide vertical channel transistors.
The device also demonstrated outstanding operational stability. Even after more than ten million cycles of harsh electrical stress testing, the threshold voltage shift remained below 50 millivolts (mV), confirming its high reliability as a memory device.
The team further evaluated system-level performance by integrating conventional silicon CMOS technology with the new oxide semiconductor platform. The results suggest that this approach could significantly improve the performance of next-generation compute-in-memory (CIM) systems, intelligent semiconductors that perform AI computation directly inside memory.
Hyeonho Gu, the first author of the study, said, “This research is significant because it goes beyond improving memory density and addresses the long-standing instability problem in 3D devices through a new approach based on oxygen migration control.” He added, “We expect this technology to play a key role in accelerating the commercialization of ultra-low-power, high-performance compute-in-memory systems required for the AI era.”
This study was led by KAIST researcher Hyeonho Gu as the first author and was published on May 20 in Advanced Functional Materials, a leading international journal in materials science. The paper was also selected as a Front Cover article in recognition of its academic significance and originality.
Paper title: Oxygen-Tunnel Indium Tin Oxide Vertical Channel Transistors with Enhanced Current Density and Reliability for Monolithic 3D Compute-In-Memory Systems
DOI: https://doi.org/10.1002/adfm.202531989
Author information: Hyeonho Gu (KAIST, first author); Yongwoo Lee (KAIST, corresponding author); Haksoon Jung (KAIST, corresponding author); Jimin Kwon (KAIST, corresponding author); Hoichang Jeong (UNIST, co-author); Yanfeng Zhao (UNIST, co-author); Heesoo Yang (UNIST, co-author); Minho Park (UNIST, co-author); Hyeonjin Lee (UNIST, co-author); Seunghun Baek (UNIST, co-author); Minju Song (UNIST, co-author); Junghwan Kim (UNIST, co-author); Youngmin Jo (KAIST, co-author); Hyunjin Park (Korea Research Institute of Chemical Technology, co-author); Munhyeon Kim (Seoul National University of Science and Technology, co-author); Jae-Joon Kim (Seoul National University, co-author); Kyuho Jason Lee (Yonsei University, co-author); and Byungjo Kim (UNIST, co-author).
This research was supported by the National Semiconductor Laboratory Program and the Excellent Young Researcher Program of the National Research Foundation of Korea, funded by the Ministry of Science and ICT; the Broadcast and Telecommunications Industry Technology Development Program of the Institute of Information & Communications Technology Planning & Evaluation; and the Super Gap Technology Development Program of the Korea Evaluation Institute of Industrial Technology, funded by the Ministry of Trade, Industry and Energy.
2026.08.20 View 2722 -
KAIST Develops Semiconductor Neuron That Tunes Noise to Selectively Process Signals
In electronic devices, irregular fluctuations in signals are generally referred to as “noise.” Because noise interferes with accurate information processing, conventional semiconductor technology has mainly treated it as something to be reduced or eliminated. However, neurons in the human brain do not respond in exactly the same way every time, even to the same stimulus. Tiny internal variations in neurons change when and how often neurons are fired, and this probabilistic operation is one of the brain’s key information-processing features. Inspired by this, KAIST researchers have developed a next-generation semiconductor technology that does not remove current noise generated in memristors, but instead tunes it to a desired level and uses it to process different types of signals.
KAIST (President Choongsik Bae) announced on the August 16 that a research team led by Professor Kyung Min Kim from the Department of Materials Science and Engineering has developed a new neuromorphic neuron technology that uses noise generated in semiconductor devices for information processing, enabling selective encoding of time-series signals across different frequency bands.
※ Neuromorphic technology: A technology that processes information by mimicking the way the human brain and neurons operate.
In general, noise generated in semiconductors is regarded as an obstacle to accurate signal processing. For this reason, most electronic devices are designed to reduce or eliminate noise as much as possible. The human brain, however, works differently. Neurons, the nerve cells of the brain, do not always respond in the same way to the same stimulus because of internal probabilistic fluctuations. This irregularity actually helps the brain flexibly respond to a wide range of situations and sensory signals.
The research team used a memristor in this study. A memristor is a semiconductor device that changes its resistance state in response to electrical stimulation and remembers that state. Until now, current noise generated in memristors has mainly been used for random number generation, which creates unpredictable numbers, or for probabilistic computing.
However, previous studies have largely focused on using the inherent randomness of memristors as it is. Technologies that can tune probabilistic response characteristics according to need had not been sufficiently realized.
The key insight of this study is that when the resistance state of a memristor is changed, the magnitude and behavior of its current noise also change. By presetting the resistance state of the memristor, the probability of spike generation and the response range can vary even under the same input. Using this principle, the research team implemented a “programmable probabilistic neuron (PPN)” that treats noise not simply as instability, but as an information-processing resource that can be tuned in a desired way.
This neuron can be configured to respond differently depending on how rapidly an input signal changes, in other words, its frequency. By changing only the resistance state of the memristor, the same circuit can be switched to respond sensitively to slow human activity signals in the hertz (Hz) range or fast speech signals in the kilohertz (kHz) range. Hz and kHz are units that indicate how many times a signal repeats per second, with 1 kHz equal to 1,000 Hz.
In simple terms, a single artificial neuron can be reconfigured according to the speed of the signal it needs to process. When processing slowly changing signals such as human movement, it can operate in a way suited to slow variations; when processing rapidly changing signals such as speech, it can be adjusted to capture short and fast changes effectively.
The research team verified the technology using signals with different frequency ranges. The system encoded and classified human activity signals in the Hz range and speech signals in the kHz range, achieving accuracies of 94.8% in human activity recognition and 95.0% in speech recognition.
Professor Kyung Min Kim said, “The significance of this study lies in demonstrating that memristor noise can be harnessed as a tunable information-processing resource, rather than simply treated as an error or instability,” adding, “Because the same hardware can be reconfigured for signals of different speeds and frequencies, it could be used as a signal-processing technology for future low-power edge neuromorphic systems.”
This study was led by Dr. Do Hoon Kim from the Department of Materials Science and Engineering as first author, and was published in the internationally renowned materials science journal Advanced Materials on August 05.
Paper title: Noise-Tunable Memristor Enabling Programmable Probabilistic Neurons for Frequency-Selective Time-Series Signal Encoding,
DOI: https://doi.org/10.1002/adma.74529
This research was supported by the Basic Research Program in Science and Engineering and the PIM Artificial Intelligence Semiconductor Core Technology Development Program of the Ministry of Science and ICT and the National Research Foundation of Korea.
2026.08.18 View 3518 -
KAIST Develops ‘Chameleon AI Semiconductor’ with Programmable Response Speeds
AI semiconductors are becoming more programmable. KAIST researchers have developed a device whose response characteristics can be programmed to process data changing at different speeds. The technology reduced prediction errors for time-varying data by up to 40-fold and is expected to enhance real-time AI performance in autonomous vehicles, robots, and wearable devices.
KAIST (President Choongsik Bae) announced on August 7 that a research team led by Chair Professor Shinhyun Choi from the School of Electrical Engineering and the Graduate School of Semiconductor Technology has developed a programmable dynamic memtransistor (PDM), a semiconductor device whose time-response characteristics can be adjusted to multiple states and retained, as well as an integrated array based on the device.
A memtransistor is a next-generation semiconductor device that combines the information-storage function of memory with the computing function of a transistor. In the developed PDM, the ability to process data while retaining previous information allows its response characteristics to be adjusted and retained for incoming data.
Today’s computers and smartphones require complex software processing to analyze data that changes over time, resulting in large computational loads and high power consumption. To address this, researchers have been studying technologies that allow semiconductor hardware itself to process data directly. However, conventional devices have had fixed response speeds that cannot be changed once the device is fabricated.
The research team overcame this limitation by introducing a dual-layer structure inside the transistor, combining a charge storage layer that accumulates and processes data with an electron trapping layer that controls the response speed in a nonvolatile manner.
In the PDM developed by the research team, incoming data is processed in the charge storage layer, while the electron trapping layer controls, across multiple levels, the recovery speed at which the semiconductor returns to its original state. In experiments, the team succeeded in tuning the current recovery time over an approximately 5-fold range and the characteristic frequency over a range of more than 10-fold.
In particular, in experiments involving the prediction of data in which fast and slow changes are intricately mixed, the PDM reduced prediction errors by as much as 40 times compared with conventional fixed-response semiconductor devices. The PDM enables accurate information processing even when handwriting or object-movement speeds vary, by using response characteristics configured to match different input timescales. Once the response characteristics are set, the device remembers them without requiring a continuous external power supply, and it does not require complex preprocessing of input data. Because it is fully compatible with materials used in widely adopted commercial semiconductor processes, it is also highly advantageous for mass production and commercialization.
The research team fabricated a PDM array and used it to predict complex data, confirming that it achieved accuracy comparable to conventional software-based systems while consuming far less energy.
“This study demonstrates an AI semiconductor whose response characteristics can be programmed to efficiently process data changing at different speeds,” said Chair Professor Choi. “We expect it to become a core technology that improves the performance of AI devices such as autonomous vehicles, robots, and wearables while reducing their power consumption.”
This research was led by KAIST Graduate School of Semiconductor Technology Ph.D. candidate Dae-won Kim as the first author, with Yoonho Cho, Seokho Seo, Yujin Kim, See-On Park, Taehwan Jang, and Chaebin Park participating as co-authors. Young Taek Oh and Fellow Jae-Duk Lee of Samsung Electronics’ Semiconductor R&D Center also participated as co-authors, and Chair Professor Shinhyun Choi served as the corresponding author. The research was published in July in the internationally renowned journal Nature Communications on July 4.
Paper title: Programmable memtransistor array with temporal dynamics modulation for efficient time-series data processing,
DOI: https://doi.org/10.1038/s41467-026-75211-5
This research was supported by the National R&D Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT, the ETRI R&D Support Program of the Institute of Information & Communications Technology Planning & Evaluation, the HRD Program for Industrial Innovation of the Korea Institute for Advancement of Technology funded by the Ministry of Trade, Industry and Energy, Samsung Electronics, and others.
2026.08.07 View 4504 -
KAIST Develops Low-Temperature Technique for Growing Crystal-Aligned Semiconductor Films
Building next-generation semiconductors and low-power electronic devices requires precisely stacking materials with different functions. In this process, it is essential to preserve each material's intrinsic properties, as well as the interface where the two materials meet, without damage. Layered van der Waals materials, including transition metal dichalcogenides (TMDs), have attracted considerable attention as next-generation semiconductor platforms because their layers interact through weak forces, enabling different materials to be stacked while maintaining atomically clean interfaces.
KAIST (President Choongsik Bae) announced on the 27th of July that a research team led by Professor Joonki Suh from the Department of Chemical and Biomolecular Engineering, in collaboration with Professor Bonggeun Shong's team at Hanyang University and Professor Yimo Han's team at Rice University in the United States, has developed a new semiconductor manufacturing technique based on atomic layer deposition (ALD). ALD is a thin-film deposition process in which semiconductor precursor are supplied sequentially, enabling uniform thin films to be deposited with atomic-level control over their thickness.
The research team focused on van der Waals materials. These two-dimensional semiconductor materials consist of multiple atomic layers held together by weak interlayer forces, allowing them to be peeled apart into sheets as thin as paper. Because different materials can be freely stacked, van der Waals materials are attracting attention as key building blocks for next-generation AI chips and ultra-low-power semiconductor devices.
However, their chemically stable surfaces make it difficult to grow new semiconductor layers in a uniformly aligned orientation. This challenge becomes even greater at lower temperatures, where atoms tend to nucleate and grow in random directions, making it difficult to produce high-performance semiconductor films.
The research team developed a new method that allows tellurium (Te)-containing precursors—molecular building blocks used to fabricate semiconductors—to move freely across the surface, find the most energetically stable positions, and form a thin film.
Tellurium is attracting attention as a key material for next-generation semiconductors and optoelectronic devices, including photodetectors and light-emitting diodes (LEDs), because it combines highly direction-dependent electrical conductivity with excellent light-controlling properties.
Using this approach, the research team succeeded in achieving epitaxial growth of tellurium uniformly in a single direction on van der Waals materials— next-generation two-dimensional semiconductor materials composed of multiple atomically thin layers stacked like sheets of paper— at a low temperature of 150°C using ALD. In epitaxial growth, a new semiconductor film grows in an ordered manner following the atomic arrangement of the underlying crystal, enabling the precise fabrication of high-quality semiconductor films. This process is comparable to stacking bricks neatly in the same direction rather than placing them randomly, which can improve electrical transport and enhance semiconductor performance.
The researchers also confirmed that the technology could be applied to a range of van der Waals materials, including tungsten diselenide (WSe2), molybdenum disulfide (MoSS), rhenium diselenide (ReSe2), and mica. This demonstrates that the method is not limited to a single material but can be broadly used with various next-generation semiconductor materials.
The team further used the resulting semiconductor films to fabricate transistors, key semiconductor devices that control the flow of electrical current, as well as optoelectronic devices that detect or emit light. This demonstrated that the new manufacturing technology is not confined to laboratory-scale material growth but can also be applied to the fabrication of functional semiconductor devices.
"This study is the first to demonstrate that high-quality semiconductor films can be grown on van der Waals materials at low temperature without damaging the underlying materials," said Professor Suh. "We expect this technology to serve as a key manufacturing platform for integrating a wide range of next-generation semiconductors on a single chip," he added.
The study, with Changhwan Kim, a doctoral student, as first author and Professor Suh as corresponding author, was published in the journal Science Advances on July 24.
Paper title: Van der Waals template-encoded soft epitaxy of tellurium enabled by atomic layer deposition
DOI: 10.1126/sciadv.aef1430
Author information: Changhwan Kim (Korea Advanced Institute of Science and Technology / Ulsan National Institute of Science and Technology, first author) and Joonki Suh (Korea Advanced Institute of Science and Technology, corresponding author)
This research was supported by the National Research Foundation of Korea, under the Ministry of Science and ICT.
2026.07.27 View 3114 -
KAIST Finds Clue to Solving the “Electrical Bottleneck” in Semiconductors
When the pathways through which electricity flows inside a semiconductor become blocked, device performance declines and power loss increases. A Korean research team has developed a new structure that could resolve this “electrical bottleneck” and, for the first time, directly confirmed that electric charges flow continuously without interruption. This achievement is expected to become a key technology for improving the performance and power efficiency of future semiconductors, including AI semiconductors and ultra-low-power semiconductors.
KAIST announced on July 13 that a research team led by Professor Seungbum Hong from the Department of Materials Science and Engineering, in collaboration with Professor Kibum Kang from the Department of Materials Science and Engineering at KAIST and Professor Sung Beom Cho’s research team at Sungkyunkwan University, has realized a new structure in which electricity flows without obstruction in a two-dimensional material—an ultrathin material only one or two atomic layers thick—that is attracting attention for next-generation semiconductor devices. The team also developed an analytical platform capable of directly observing this charge transport at the nanometer scale.
In semiconductors, contact resistance, which arises at the interface where a metal electrode meets a semiconductor, degrades performance and causes power loss. Especially as semiconductors continue to scale down, the influence of contact resistance becomes even greater, making it one of the most challenging technical bottlenecks in developing next-generation semiconductors.
Instead of attaching a metal electrode on top of a semiconductor as in conventional approaches, the research team continuously formed semi-metallic and semiconducting regions within a single two-dimensional m
aterial. By creating a structure in which the two regions are naturally connected within the same material, the team demonstrated for the first time that current can flow across the boundary without being blocked.
Specifically, the team continuously implemented a semi-metallic region and a semiconducting region within a single thin film of platinum diselenide (PtSe₂), an atomically thin two-dimensional material. By realizing a monolithic structure, in which a single material is formed continuously without interruption, the team proposed a new structure that allows current to flow across the boundary without obstruction.
Using Atomic Force Microscopy (AFM), a microscope that uses a probe to measure surface and electrical properties down to the atomic level, the team directly visualized charge transport inside the thin film at the nanometer scale.
As a result, the team confirmed for the first time that, when current moved from the semi-metallic region to the semiconducting region, the flow continued naturally without an “electrical bottleneck,” such as a blockage or bending of the current path. This is the first experimental demonstration that a monolithic interface does not interfere with current flow.
Furthermore, the team verified device operation by applying an electric field to the semiconducting region. The results confirmed that current flow can be stably controlled in a metal–semiconductor junction structure, demonstrating the potential of the structure for next-generation electronic devices.
This study presents a source technology that can dramatically reduce contact resistance in next-generation semiconductor devices based on two-dimensional materials. It is expected to be widely applicable to the development of future semiconductor technologies, including AI semiconductors, ultra-low-power semiconductors, and next-generation logic semiconductors.
The study was co-first-authored by Yeongyu Kim, a Ph.D. candidate and Dr. Minseung Gyeon from the Department of Materials Science and Engineering at KAIST; and Ji Hoon Hong, a Ph.D. candidate at Sungkyunkwan University. The work was published in the July 2026 issue of Matter, an international journal in the field of materials science.
※ Paper title: Nanoscale imaging of charge transport across the semimetal-semiconductor interface in monolithic platinum diselenide
DOI:https://doi.org/10.1016/j.matt.2026.102873
This research was supported by the STEAM Research Program and the Nanomaterials Technology Development Program of the Ministry of Science and ICT and the National Research Foundation of Korea.
2026.07.13 View 2097 -
KAIST Automates the Search for “Dream Semiconductor” 2D Semiconductors
The era of researchers manually searching for two-dimensional semiconductors, which are drawing attention as next-generation AI semiconductors, is coming to an end. KAIST researchers have automated semiconductor screening and device fabrication, analyzed thousands of devices, and revealed the relationship between thickness and performance that had long been difficult to identify. This achievement is expected to shift next-generation semiconductor research toward a data-driven approach and accelerate the commercialization of AI semiconductors and ultra-low-power semiconductors.
KAIST (President Choongsik Bae) announced on the 9th that a research team led by Professor Jimin Kwon of the School of Electrical Engineering and the Department of AI System has developed a technology that automatically identifies two-dimensional semiconductors from optical microscope images alone and connects the process to transistor fabrication, through joint research with UNIST, Hanbat National University, Hanyang University, and Washington University in St. Louis in the United States.
Two-dimensional semiconductors are ultrathin semiconductors only a few atomic layers thick. They are called “dream semiconductors” because they can enable smaller semiconductors that consume less electricity than conventional silicon semiconductors. Today’s silicon semiconductors are approaching physical limits, as continued miniaturization of circuits leads to greater power loss and heat generation. Two-dimensional semiconductors, which are attracting attention as next-generation materials to overcome these limits, are expected to be used in a wide range of future technologies, including AI semiconductors, smartphones, data centers, wearable devices, foldable or stretchable electronics, and ultra-small medical sensors.
However, in two-dimensional semiconductors made through solution processing, the position, size, and thickness of each small semiconductor flake all differ, requiring researchers to find the desired samples one by one under a microscope. They then had to manually design electrodes according to the identified positions, requiring substantial time and effort, and making it practically difficult to analyze thousands or more devices at once.
The research team used molybdenum disulfide (MoS₂), a representative two-dimensional semiconductor material. By using the fact that the RGB red, green, and blue brightness values seen under a microscope change depending on thickness, the team enabled a computer to automatically identify the desired semiconductor and automatically design the electrodes. Verification using atomic force microscopy (AFM) confirmed that even subtle thickness differences of three to eight layers could be accurately distinguished.
Through this approach, the team successfully selected suitable samples automatically from more than 120,000 semiconductor flakes and fabricated and analyzed 1,615 transistors.
The large-scale analysis also produced meaningful results. The team statistically clarified for the first time that as the semiconductor becomes thicker, current flows more easily, but the ability to switch electricity on and off actually decreases. This characteristic had been difficult to confirm previously because only a small number of samples could be analyzed, but the team revealed it through large-scale data.
The greatest significance of this study is that it did not simply automate the fabrication process, but transformed two-dimensional semiconductor research, which had relied on human experience, into data-driven research. Going forward, the technology is expected to enable researchers to fabricate and analyze more semiconductors more quickly, identify high-performance materials, and ultimately expand into research in which AI designs new semiconductors.
This study was conducted with Professor Jimin Kwon, Dr. Haksoon Jung, and Dr. Yongwoo Lee of KAIST as co-corresponding authors, and Sanghyun Lee of UNIST as the first author. The research results were published on April 3 in Advanced Functional Materials, a leading international journal in materials science, and were also selected as an Inside Back Cover article in the field of 2D Materials & Electronics.
※ Paper title: Statistically Resolving Thickness-Dependent Electrical Characteristics in Multilayer-MoS₂ Transistors, DOI: 10.1002/adfm.202532204
※ Author information: Professor Jimin Kwon (KAIST, corresponding author), Dr. Haksoon Jung (KAIST, corresponding author), Dr. Yongwoo Lee (KAIST, corresponding author), Sanghyun Lee (UNIST, first author), and participating researchers from partner institutions: Sumin Hong (UNIST), Minho Park (UNIST), Professor Seongju Kim (Hanbat National University), Professor Sang-Hoon Baek (Hanyang University), Professor Joonki Suh (KAIST), Seonguk Yang (KAIST), Professor Sang-Hoon Bae (Washington University in St. Louis), and Dr. Chang-Soo Lee (TDS)
This research was supported by the Individual Basic Research Program of the National Research Foundation of Korea (NRF), funded by the Ministry of Science and ICT (MSIT), and by the Advanced Strategic Industry Super-Gap Technology Development Program of the Korea Planning & Evaluation Institute of Industrial Technology (KEIT), funded by the Ministry of Trade, Industry and Energy (MOTIE).
2026.07.09 View 3959 -
How Small Can Semiconductors Get? KAIST Develops Atomic-Level Prediction Technology
<(From Left) Dr. Tae Hyung Kim, Dr. Juho Lee, (Upper Left) Professor Yong-Hoon Kim>
As the global semiconductor industry enters the so-called "2 nm (nanometer, one-billionth of a meter) process" era, the actual size of transistors — the core components of semiconductor chips — still remains above 10 nm. How much smaller, then, can transistors actually get? KAIST researchers have developed a technology to predict that limit through quantum mechanical atom-level calculations.
KAIST (President Kwang Hyung Lee) announced on the 14th that a research team led by Professor Yong-Hoon Kim of the School of Electrical Engineering has developed a computational design technology that utilizes computer simulations to analyze and predict the scaling limits of transistors, a key challenge in developing next-generation semiconductor devices.
<Research Image(AI-generated)>
Transistors are ultra-small switches that turn electrical currents on and off, serving as key components that determine the performance and power efficiency of semiconductor chips that power smartphones, artificial intelligence computers, and more. The semiconductor industry has continuously downsized transistors to achieve higher performance and lower power consumption. However, when the size becomes excessively small, quantum tunneling occurs—a quantum mechanical phenomenon where electrons pass through energy barriers they normally cannot cross—making current control difficult. For this reason, identifying how much smaller transistors can be made within the boundaries of quantum tunneling is a critical task in next-generation semiconductor development.
However, it is virtually impossible to experimentally confirm the scaling limits of transistors directly. With current technology, it is difficult to precisely control and quantitatively analyze the contact area where the metal electrode and the semiconductor channel (the pathway through which current flows inside a transistor) meet at the atomic level.
The research team resolved this issue by utilizing ab initio or first-principles calculations, a method that computes material properties based solely on fundamental physics laws without relying on experimental data. The research team had previously developed and reported a new theoretical-computational framework called multi-space constrained-search density functional theory (MS-DFT), which extends the scope of first-principles calculations from materials to devices by precisely analyzing the complex quantum phenomena occurring at the interface where metal electrodes and semiconductors meet and across which electrons flow.
In this study, the team built on this framework to perform computational transfer length method (TLM) experiments, the gold standard experimental technique for extracting contact resistance (the resistance to current flow occurring at the metal electrode-semiconductor interface). Based on the atomic-level TLM calculations results, they identified the quantum tunneling limit (the length at which electrons stop leaking and begin to allow transistor current control).
The research team applied this technology to a monolayer MoS₂ (molybdenum disulfide) device, a representative two-dimensional semiconductor material that can be made as thin as an atomic layer and is a candidate material for next-generation transistor channels. As a result, they were able to quantitatively analyze how deeply electrons penetrate into the channel and how much this hinders current flow control depending on the type of metal electrode and the contact atomic geometry. In other words, they clarified that the limit to how small a transistor can be made varies depending on which metal and contact structure are selected. This implies that the performance and limits of a device can now be predicted in advance solely through computer simulations before the actual transistor fabrication.
< Analysis of Contact Resistance and Critical Tunneling Length in Two-Dimensional Semiconductors Using the First-Principles Transfer Length Method >
According to the research results, the critical tunneling length—the maximum length at which electrons penetrate into the channel and begin to affect transistor operation—was found not to be a single fixed value. This length emerged as a design variable that changes depending on the work function of the metal (the minimum energy required to remove an electron from a metal) and the contact structure of the interface where the metal and semiconductor meet. This signifies that the extent to which a transistor can be downsized depends on the combination of materials and structural design.
In particular, among the candidate metal types and contact structures considered, the research team confirmed that the length where electrons stop leaking could be reduced to less than 4 nm. This result demonstrates the possibility of making transistors even smaller than the levels achieved today.
Furthermore, the research team proposed a design strategy for next-generation semiconductor chips that reduce power consumption by combining two-dimensional semiconductors with different properties.
This study is significant because it establishes a platform for predicting scaling limits and designing optimal device configurations before actually fabricating semiconductor chips. Through this, it is expected to reduce trial and error and shorten the development period in the process of developing next-generation ultra-small AI semiconductor devices.
Professor Yong-Hoon Kim said, "This study is significant because it presents a new physical criterion for defining how small next-generation transistors can become. By computationally analyzing quantum mechanical phenomena in the sub-10 nm regime, which are difficult to probe experimentally, we have opened a path toward utilizing these findings in next-generation transistor design."
The study, in which Dr. Tae Hyung Kim participated as the first author, was published online on May 28th in the prestigious computational journal 'npj Computational Materials, a prestigious journal in the field of computational materials science ※ Title of the paper: Ab initio transfer length method simulations of tunneling limits in 2D semiconductors, DOI: https://doi.org/10.1038/s41524-026-02101-1
This research was conducted with support from programs such as the Mid-Career Researcher Program and EDISON 2.0 Program of the National Research Foundation of Korea.
2026.06.15 View 4717